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Espressif Systems /ESP32-P4 /H264_DMA /OUT_RO_STATUS_CH0

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Interpret as OUT_RO_STATUS_CH0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0OUTFIFO_RO_CNT_CH0 0OUT_RO_WR_STATE_CH0 0OUT_RO_RD_STATE_CH0 0OUT_PIXEL_BYTE_CH0 0OUT_BURST_BLOCK_NUM_CH0

Description

TX CH0 reorder status register

Fields

OUTFIFO_RO_CNT_CH0

The register stores the 8byte number of the data in reorder Tx FIFO for channel 0.
OUT_RO_WR_STATE_CH0

The register stores the state of read ram of reorder
OUT_RO_RD_STATE_CH0

The register stores the state of write ram of reorder
OUT_PIXEL_BYTE_CH0

the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes
OUT_BURST_BLOCK_NUM_CH0

the number of macro blocks contained in a burst of data at TX channel

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data